A device for single-photon detection is known as a Single Photon Avalanche Detector-SPAD [e.g. “Avalanche photodiodes and quenching circuits for single-photon detection”, S. Cova, M. Ghioni, A. Lacaita, C. Samori, and F. Zappa in APPLIED OPTICS vol. 35 No. 12, 20 Apr. 1996, and E. Sciacca, A. Giudice, D. Sanfilippo, F. Zappa, S. Lombardo, R. Concentino, C. Di Franco, M. Ghioni, G. Fallica, G. Bonanno, S. Cova, E. Rimini “Silicon Planar Technology for Single-Photon Optical Detectors”, IEEE Transactions on electron devices, vol. 50, No. 4. April 2003], and this device comprises a silicon substrate with an epitaxial layer made on it, the epitaxial layer having on a surface a small (e.g., 10-200 microns) region (e.g., a cell) of conductive type opposite to the given layer conductive type. The cell may be supplied with reverse bias that exceeds a breakdown voltage. When a photon is absorbed in this region, a Geiger discharge takes place, and such a discharge may be limited with an external quenching resistor.
Such a single-photon detector (SPAD) may comprise a very small area or volume, and may not be able to measure the light flux intensity.
In order to eliminate these defects, a large number (=103) of such cells may be used, and located on a common substrate having an area equal to or larger than 1 mm2. Respective cells work as the above described photon detector, and the device may detect light intensity proportional to the number of the worked cells.
Such type of device—the Silicon Photomultiplier (SiPM)—is described in patent RU 2004113616 with a priority of May 5, 2004 and European Patent Application EP 1 755 171 A1, published Feb. 21, 2007 “Silicon Photomultiplier (e.g., variants) and cell therefore”. The SiPM comprises a silicon substrate, a plurality of cells (the sizes of which are 20-100 microns and which are located on a surface of the substrate in an epitaxial layer); respective cells may comprise an internal individual quenching resistor made of high resistance polysilicon and may be located on top of the silicon oxide layer which covers respective cells. The main defects of this device are the following:                the usage of high resistance polysilicon quenching resistors which are not CMOS-technology compatible;        the location of polysilicon quenching resistors on top of the silicon oxide layer requires the opening of many (e.g., ˜few×103) windows in silicon oxide layer for connection of quenching resistor with entrance window silicon layer of the SiPM—that leads to the loss of the photon detection efficiency (PDE) and makes the fabrication process more complicated;        the presence of epitaxy layer gives rise to the increasing of dark rate of the SiPM and also makes the fabrication process more complicated.        
The present disclosure provides a cell for a silicon-based photoelectric multiplier which is easy and efficient to fabricate, and comprises a high efficiency of light detection while in operation. Advantageous embodiments are described herein.
The present disclosure provides a cell for a silicon based photodetector having high efficiency in a broad band of wavelengths with a coefficient of amplification up to approximately 107 at least because of increased cell sensitiveness and significantly reduced dark rate, while maintaining a framework of CMOS technology. The present disclosure may also provide a silicon based photodetector comprising a plurality of such cells.
In one embodiment, the quenching resistor in the cell of the silicon-based photoelectric multiplier may be formed in an uppermost layer of the semiconductor body. That is, for example, the quenching resistor may be formed laterally besides the upper layer of the p-n junction of the device. The quenching resistor layer may thus be comprised of a semiconductor layer connected to a lateral side face of the upper layer of the p-n junction and extends in a direction away from the p-n junction to connect the p-n junction with a voltage distribution line. The quenching resistor layer, for example, may be fabricated as a well area in the upper surface of the semiconductor body comprising a dopant concentration in order to yield a desired resistance or resistivity value to function as a quenching resistor for quenching the avalanche current. The disclosure enables integration of fabrication of the quenching resistor layer into a CMOS fabrication process.
According to one embodiment, the voltage distribution layers and/or lines may be integrated within the CMOS fabrication process. The voltage distribution lines may be fabricated as well areas into the upper surface of the semiconductor body, these well areas comprising comparably high dopant concentration to function as electrically conductive lines.
A method of fabricating a silicon-based photoelectric multiplier is illustrated in FIGS. 2 and 3 and may be performed in the form of a complete CMOS fabrication process, the fabricating of respective layers which are of functional significance of the device would be integrated in the CMOS fabrication process. In particular the process may comprise providing a silicon substrate, fabricating a first layer of a first conductivity type, fabricating a plurality of second layers of a second conductivity type, and fabricating a plurality of quenching resistor layers and voltage distribution lines, the fabrication conducted preferably by ion implantation processes. Moreover a buried layer of a first conductivity type may be fabricated by a deep ion implantation process.